Coded transmissions form part of a consolidated theory of electrical transmissions.
Basically, coding seeks to introduce a redundancy in the transmission in order to enable identification and correction of a decoding error. Redundancy implies a greater occupation of band used and higher transmission costs.
A code with memory can be viewed as a finite-state machine that receives as input K0 bits and produces as output symbols on No bits. The ratio K0/N0 takes the name of “code rate”.
The use of a system with memory involves the symbol as output from the encoder having a certain degree of correlation with the symbols that precede it. This characteristic can be exploited by the decoder in the step of estimation of the transmitted symbol.
The technical literature regarding codes is extremely extensive. The first codes to be introduced were block codes, and a particularly effective development of coding techniques is represented by convolutional codes. A convolutional code is characterized not only by the parameters N0 and K0 already mentioned previously but also by a further parameter N, which enables the number of encoder states to be determined. A convolutional code can thus be viewed as a partially connected graph of the type represented in FIG. 1. The degree of connection of the graph affects the capacity of the code to detect and correct errors.
An alternative representation of the code uses a trellis of the type represented in FIG. 2. The evolution in time of the encoded transmission can hence be viewed as proceeding along the trellis according to a particular path.
One of the most widely known coding/decoding algorithms, which for this very reason does not require any detailed presentation herein, is the algorithm known as Viterbi algorithm. A Viterbi decoder seeks to estimate the “most likely” path.
The evolution of a code, viewed as a time-discrete system, is in fact given by a response of the state, which enables calculation of the subsequent state on the basis of the knowledge of the current state and of the current input, and by a response of the output, which depends upon the current state and the current input.
The theory of electrical communications is founded upon the idea that any optimal (or sub-optimal) receiver “observes” a datum at input, seeking to maximize the a posteriori probability of the datum observed with respect to an attempt sequence. What is observed is a random quantity, linked to the presence of the given signal and the random noise due to the interference sources.
Generally, these two quantities are added algebraically, and in the literature, there has been proposed a wide variety of models of possible sources of noise. The most simple of all is white Gaussian noise (WGN), the probability density of which assumes a form that is convenient for carrying out calculations.
In different applications, in particular of earth communications, the source of interference is not additive, but instead multiplicative, with a probability distribution which, in the far from rare case of a number of sources of interference, assumes a form that is by no means easy to simplify.
The Viterbi decoder, already cited previously, is a somewhat complex circuit that carries out convolutional decoding. There exist numerous circuits for telecommunications that exploit the corresponding technique. In particular, the problem of maximization of the a posteriori probability density is seen, in a sub-optimal way, in the observation of a limited window of the trellis. The probability density is viewed as a sum of partial quantities at each step (accumulated metrics), and the Viterbi circuit constructs at each step the partial paths (i.e., the survived ones) that converge in each state of the trellis.
The optimal path passes through one of these survived paths, and, at the subsequent step, for each state of the trellis, the Viterbi decoder selects the 2Ko survived paths that converge in the state considered. For each of these, it calculates the new metrics as sum of the previous metrics, plus the individual contribution (branch metrics) due to the transition to the state considered from the step prior to the current one.
The new survived path will be the one that, between the 2Ko survived paths, will have totalized a maximum, or minimum, metric. The theory of the maximum-likelihood decision involves in fact maximization of the a posteriori probability. According to the structure of the statistics of the signal received, the maximization of this probability may involve the search for the maximum or minimum metric (for example, according to a sign which can modify the direction of the search).
The use of a Viterbi decoder entails some difficulties of implementation. The operation of a Viterbi decoder can be viewed as being such as to involve the application of three operations:                the sum between the accumulated metric and the branch metric (addition function or ADD);        a comparison for choosing the maximum metric (comparison function or COMPARE); and        the selection of the optimal survived path (selection function or SELECT).        
From the standpoint of the circuit construction (see FIG. 3), this usually involves the use of two adder blocks A1, A2, a comparator block C, and a selector block S. The corresponding outputs are constituted by a first line that goes from the selector S to the block SMS for updating the metric of the states (FIG. 4) and by a second line that goes from the output of the comparator C to the block SPS for storage of the survived paths (not illustrated in FIG. 3 but shown in FIG. 4).
The complex of elements illustrated, which forms what is commonly referred to as an add-compare-select (ACS) unit, operates with a floating-point arithmetic (such as IEEE-754) on 64 precision bits.
There is then required a circuit that calculates the branch metrics, a trellis, and finally, a circuit for updating the trellis, which is commonly referred to as TRACEBACK.
The architecture of a traditional Viterbi decoder is reproduced in FIG. 4. In the corresponding block diagram, there may be seen the ACS unit, illustrated in detail in FIG. 3, together with the memory for the metric of the states SMS, the branch metric circuit BM, and the memory for the survived paths SPS. There is also provided a generator of the decoded output sequences, designated by G. These blocks are combined with an input interface block IIB, an output interface block OIB, and a control block CB.
The Viterbi circuit is one of the most widely known solutions, and this fact renders superfluous any detailed description of the mode of interaction between the various blocks represented in FIG. 4. What is interesting to note in the context of the present description is that the architecture represented in FIG. 4 involves a very considerable consumption of resources in terms of area occupied and power absorption.
The performance of a Viterbi decoder usually depends upon the selection of the calculation of the branch metric, which is in turn linked to the model of random process by which the signal received is represented. Operating on a Gaussian channel, the metric usually considered to be best is the Euclidean one.
Since it has been developed paying significant attention to disturbance represented by additive white Gaussian noise (AWGN), the performance of the Viterbi decoder is to a certain extent impaired in the application in a noisy environment affected by fading phenomena and/or multipaths.
For reasons that will become clear in what follows, it is convenient at this point to refer to another well-known classic circuit in the sector of communications technology (and not only communications technology), namely, the circuit commonly referred to as phase-locked loop (PLL). The basic scheme of a classic PLL (a circuit which originally appeared in the analogical-electronics sector, for example for detecting carriers in analogical modulations, generating or aligning sync signals, controlling the speed of rotating members, and the like) is given in FIG. 5.
The main components of a classic PLL are represented by a phase detector PD, a loop filter H, and a voltage-controlled oscillator VCO. Basically, the phase detector PD has the task of extracting the phase difference between the two waveforms at its inputs, constituted, respectively, by a signal S(t) to be locked and by a signal at output V(t) from the oscillator VCO. A possible architecture of the phase detector PD envisages the presence of a multiplier and a low-pass filter set cascaded to one another. At output from the multiplier there is a dc component proportional to the cosine of the phase difference, and a component with a frequency 2ω, which is to be eliminated by the low-pass filter.
The oscillator VCO is an oscillator of which the instantaneous oscillation frequency can be controlled as a function of an input signal. In the example illustrated herein, the signal which drives the VCO is the signal F(t) present at output from the filter H. This is usually a low-pass filter of order N (number of stable poles), which identifies also the order of the PLL.
The corresponding literature is extremely extensive and covers a practically infinite range of possible variants of embodiment, comprising non-linear and/or partially or totally digital implementations. Essentially, it will suffice to recall that in a scheme like the one represented in FIG. 5, the input signal, which can be expressed in general as:S(t)=V0 cos(ωt+α(t))is compared with the reference oscillation coming from the oscillator VCO:V(t)=VVCO cos(ωt+β(t)
The low-pass filter H produces at output a signal proportional to the phase difference between the two signals:F(t)=Vcos(α(t)−β(t))which can trigger within the PLL a negative reaction such as to cause it to lock, in the steady-state condition, the phase of the input signal, i.e., with β(t) substantially equal to α(t).
As has already been said, the technical literature on the subject of PLLs (also for applications only marginally related to phase and/or frequency locking of an input signal) is in effect vast. By way of example, U.S. Pat. Nos. 4,482,869; 4,584,695; 4,609,886; 5,666,387; 5,943,382; 6,167,245; 6,359,949; 6,396,354; and 6,542,038 and the article by M. P. Fitz: “A Bit Error Probability Analysis of a Digital PLL Based Demodulator of Differentially Encoded BPSK and QPSK Modulation”, IEEE Trans. on Communications, vol. 42, No. 1, January 1994, all address the subject of PLLs and the design and use of PLLS.